The present invention relates generally to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a NAND flash memory device.
In order to manufacture a highly-integrated semiconductor memory device, fine patterns have been formed on a semiconductor substrate. Due to these fine patterns, various process failures occur. For example, a NAND flash memory device comprises of a stacked gate on a semiconductor substrate, which includes a tunnel insulating layer, a charge storing layer, a dielectric layer, and a control gate layer. The stacked gate is generally formed by a method described below.
A tunnel insulating layer and a charge storing layer are deposited on the semiconductor substrate, which includes active regions divided by isolation regions. The isolation regions of the semiconductor substrate may be exposed by etching the charge storing layer and the tunnel insulating layer.
Trenches are formed in the semiconductor substrate by etching the exposed isolation regions of the semiconductor substrate, and isolating layers are formed in the trenches. As a result, the active regions are divided by the isolation layers, and the tunnel insulating layer and the charge storing layer collectively are divided by the isolation layers and remain on the active regions.
A dielectric layer and the control gate layer are deposited on the entire structure, including on the isolation layers. Subsequently, gate mask patterns are formed on the control gate layer in a direction crossing the isolation layers and the active regions, and thus the control gate layer, the dielectric layer, and the charge storing layer are etched by using the gate mask patterns as an etch barrier. As a result, the charge storing layer on the active regions is divided into a plurality of charge storing layer segments. Additionally, control gate layer line patterns applied in a direction crossing the active regions and the isolation layers form patterns on the charge storing layer.
According to the aforementioned conventional art, the trenches are defined by an etched region from the charge storing layer to the semiconductor substrate. Therefore, the aspect ratio for each trench is high. Pattern failure, such as generation of a void, may thus occur. Due to higher integration, the aspect ratio for each trench increases, causing greater difficulties to form patterns.